Efficient and Composable Masked AES S-Box Designs Using Optimized Inverters. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2025, n. 1, p. 656–683, 2024. DOI: 10.46586/tches.v2025.i1.656-683. Disponível em: https://ojs.ub.rub.de/index.php/TCHES/article/view/11942.. Acesso em: 23 dec. 2024.