Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2024, n. 4, p. 179–204, 2024. DOI: 10.46586/tches.v2024.i4.179-204. Disponível em: https://ojs.ub.rub.de/index.php/TCHES/article/view/11788.. Acesso em: 23 dec. 2024.