New Circuit Minimization Techniques for Smaller and Faster AES SBoxes. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2019, n. 4, p. 91–125, 2019. DOI: 10.13154/tches.v2019.i4.91-125. Disponível em: https://ojs.ub.rub.de/index.php/TCHES/article/view/8346.. Acesso em: 23 dec. 2024.